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ISL5216
Pin Descriptions
(Continued)
NAME
SYNCI3
SYNCO
RESET
JTAG
TDO
TDI
TMS
TCLK
TRST
OUTPUTS
SD1A
SD2A
SD1B
SD2B
SD1C
SD2C
SD1D
SD2D
SCLK
SYNCA
SYNCB
SYNCC
SYNCD
TYPE
I
O
I
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
Synchronization input signal for channel 3. Same functions as SYNCI but connects only to channel 3. This pin
is internally pulled low to allow it to be left unconnected.
Synchronization Output Signal. The processing of multiple ISL5216 or HSP50216 devices can be
synchronized by tying the SYNCO from one ISL5216 device (the master) to the SYNCI of all the
ISL5216/HSP50216 devices (the master and slaves).
Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values.
Test data out
Test data in. Contains weak internal pull-up.
Test mode select. Contains weak internal pull-up.
Test clock. Contains weak internal pull-down.
Test reset. Active low. Contains weak internal pull-down.
Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2,
magnitude, phase, frequency (d φ /dt), AGC gain, and/or zeros. In addition, data outputs from Channels 0, 1, 2
and 3 can be multiplexed into a common serial output data stream. Information can be sequenced in a
programmable order. See Serial Data Output Formatter Section and Microprocessor Interface Section.
Serial Data Output 2A. This output is provided as an auxiliary output for Serial Data Output 1A to route data to
a second destination or to output two words at a time for higher sample rates. SD2A has the same
programmability as SD1A except that floating point format is not available. See Serial Data Output Formatter
Section and Microprocessor Interface Section.
Serial Data Output 1B. See description for SD1A.
Serial Data Output 2B. See description for SD2A.
Serial Data Output 1C. See description for SD1A.
Serial Data Output 2C. See description for SD2A.
Serial Data Output 1D. See description for SD1A.
Serial Data Output 2D. See description for SD2A.
Serial Output Clock. Can be programmed to be at 1, 1/2, 1/4, 1/8, or 1/16 times the clock frequency. The
polarity of SCLK is programmable.
Serial Data Output 1A sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCA is programmable.
Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCB is programmable.
Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCC is programmable.
Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCD is programmable.
MICROPROCESSOR INTERFACE
P(15:0)
ADD(2:0)
WR
or
DSTRB
I/O
I
I
5
Microprocessor Interface Data bus. See Microprocessor Interface Section . P15 is the MSB.
Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section . Note: ADD2
is not used but designated for future expansion.
Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control, μ P
MODE, is a low data transfers (from either P(15:0) to the internal write holding register or from the internal write
holding register to the target register specified) occur on the low to high transition of WR when CE is asserted
(low). When the μ P MODE control is high this input functions as a data read/write strobe. In this mode with
RD/WR low data transfers (from either P(15:0) to the internal write holding register or from the internal write
holding register to the target register specified) occur on the low to high transition of Data Strobe. With RD/WR
high the data from the address specified is placed on P(15:0) when Data Strobe is low. See Microprocessor
Interface Section .
FN6013.3
July 13, 2007
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